Low Hardware Complexity QCA Decoding Architecture Using Inverter Chain
Jun‐Cheol JeonDepartment of Computer Engineering, Kumoh National Institute of Technology 61, Daehak-ro, Gumi, Gyeongbuk 730-701, Korea
2016en
ABI
Abstract
This paper presents a quantum-dot cellular automata (QCA) 3-8 decoder with low hardware complexity. The proposed architecture is based on inverter chains to get inverse value and cross over a wire. We also use 5-input majority voting gates for 3-input AND gates. In this paper, we focus on the hardware complexity to reduce the number of cells and minimize wasting an area. Our architecture has not only an excellent regularity and scalability but a strong signal strength so that it is easy to extend a structure and connect with other circuit.
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Cited by 20 references