Extreme scaling enabled by 5 tracks cells: Holistic design-device co-optimization for FinFETs and lateral nanowires
M. Garcia BardonInteruniversitair Micro-Elektronica Centrum, Leuven, Vlaams-Brabant, BEYasser SheraziImec, Leuven, BelgiumP. SchuddinckImec, Leuven, BelgiumDoyoung JangImec, Leuven, BelgiumDmitry YakimetsImec, Leuven, BelgiumPeter DebackerImec, Leuven, BelgiumRogier BaertImec, Leuven, BelgiumHans MertensImec, Leuven, BelgiumMustafa BadarogluQualcomm assignee at imec, Leuven, BelgiumA. MocutaImec, Leuven, BelgiumNaoto HoriguchiImec, Leuven, BelgiumD. Mocutaimec, Kapeldreef 75, 3001 Leuven, BelgiumPrasanth RaghavanImec, Leuven, BelgiumJulien RyckaertImec, Leuven, BelgiumA. SpessotImec, Leuven, BelgiumDiederik VerkestInteruniversitair Micro-Elektronica Centrum, Leuven, Vlaams-Brabant, BEAn SteegenImec, Leuven, Belgium
2016en
ABI
Abstract
By optimizing design rules, layout, devices and parasitics, we show how 5 Tracks standard cells with one fin can be enabled. This reduces area by 16% without pitch scaling and provides 34% energy gain from 6T cells. The loss in speed of 15% can be recovered by different front-end solutions. Air gap spacers are the most efficient booster and provide an extra 16% gain in energy. Lateral Nanowires can compete in speed with FinFETs with an extra energy gain of 12% if tight vertical pitch of 10 nm between wires can be achieved.
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Cited by 20 references