Self-Checking Discrete Device Synthesis Using Parity Code Properties and Self-Duality Boolean Functions

Abstract: The paper demonstrates that the established organizational structure of the concurrent error-detection circuit, founded on the self-duality feature with preliminary signal compression from the diagnostic object employing the parity function (a modified parity control structure), enables the comprehensive self-checking discrete devices for specific initial objects. As demonstrated, when conducting control checking calculations based on the self-duality feature with preliminary compression of signals from the diagnostic object by parity, faults in the modulo-2 addition gates of the parity code encoder are not detected. This is provided that the parity of the sub-vector of the data vector, generated at outputs connected by paths with the failed gate, remains unchanged. This imposes certain restrictions on the use of the established modified parity control structure in the self-checking discrete device synthesis. The paper presents a further modification to the parity testing structure. The proposed structure overcomes the known structure’s drawback by ensuring calculation control through both parity and assigning the function describing the control output to the class of self-dual Boolean functions. Due to the minor complication of the CED circuit compared to the parity check circuit, it is possible to significantly improve the testability characteristics. Further studies of the new organization structure of CED parity check circuits will allow us to determine the criteria of its applicability in the self-checking discrete device synthesis.

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