Статья

LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation Environments

Aibin YanSchool of Computer Science and Technology, Anhui University, Hefei, ChinaZhixing LiSchool of Computer Science and Technology, Anhui University, Hefei, ChinaJie CuiSchool of Computer Science and Technology, Anhui University, Hefei, ChinaZhengfeng HuangSchool of Microelectronic, Hefei University of Technology, Hefei, ChinaTianming NiCollege of Electrical Engineering, Anhui Polytechnic University, Wuhu, ChinaPatrick GirardLaboratory of Informatics, Robotics and Microelectronics of Montpellier, University of Montpellier/CNRS, Montpellier, FranceXiaoqing WenGraduate School of Computer Science and Systems Engineering, Kyushu Institute of Technology, Kitakyushu, Fukuoka, Japan

2022en

ABI

Аннотация

In deep nano-scale and high-integration CMOS technologies, storage circuits have become increasingly sensitive to charge-sharing-induced multiple-node-upsets (MNUs) that include double, triple, and quadruple node-upsets. Currently, verifications for error recovery of existing latches highly rely on EDA tools with complex error-injection combinations. In this article, a latch design protected against MNUs in the harsh radiation as well as an algorithm-based verification process is proposed. Due to the constructed redundant feedback loops, the latch can completely recover from any MNU. Algorithm-based verification and simulations both demonstrate the MNU recovery of the proposed latch. Simulation results demonstrate the low area overhead of the proposed latch compared with the only one existing of the same type.

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Идентификаторы

DOI: 10.1109/tcad.2022.3213212

Цитирования и источники

Цитирований: 2Использованных источников: 0

Показатели — AkademScholar