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Single Crystal Nanowire Vertical Surround-Gate Field-Effect Transistor

Hou T. NgCenter for Nanotechnology, NASA Ames Research Center, Moffett Field, California 94035Jin‐Woo HanCenter for Nanotechnology, NASA Ames Research Center, Moffett Field, California 94035Toshishige YamadaCenter for Nanotechnology, NASA Ames Research Center, Moffett Field, California 94035Peggy NguyenCenter for Nanotechnology, NASA Ames Research Center, Moffett Field, California 94035Yi P. ChenCenter for Nanotechnology, NASA Ames Research Center, Moffett Field, California 94035M. MeyyappanCenter for Nanotechnology, NASA Ames Research Center, Moffett Field, California 94035
2004en
ABI

Аннотация

Harnessing the potential of single crystal inorganic nanowires for practical advanced nanoscale applications requires not only reproducible synthesis of highly regular one-dimensional (1D) nanowire arrays directly on device platforms but also elegant device integration which retains structural integrity of the nanowires while significantly reducing or eliminating complex critical processing steps. Here we demonstrate a unique, direct, and bottom-up integration of a semiconductor 1D nanowire, using zinc oxide (ZnO) as an example, to obtain a vertical surround-gate field-effect transistor (VSG-FET). The vertical device structure and bottom-up integration reduce process complexity, compared to conventional top-down approaches. More significantly, scaling of the vertical channel length is lithographically independent and decoupled from the device packing density. A bottom electrical contact to the nanowire is uniquely provided by a heavily doped underlying lattice-match substrate. Based on the nanowire-integrated platform, both n- and p-channel VSG-FETs are fabricated. The vertical device architecture has the potential for use in tera-level ultrahigh-density nanoscale memory and logic devices.

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