Design of Hybrid Sorting Unit

Sorting is the fundamental function of any process for most of the application, The widely used hardware sorting algorithm in VLSI are Bitonic merge sort and Bitonic odd even sort with 24 and 19 comparator unit. In this paper a new sorting algorithm (Hybrid sort) is proposed which has 23 comparator units and provides the better performance than existing one when the bit width of input increases. The pipelining concept is applied along with parallel processing to the entire hardware sorting algorithm which improved processing time of the sorting. The proposed system used three stages of the pipeline; therefore, the speed is increased three times more than the existing method. Experiment results shows that the proposed sorting unit gives better performance when the bit width of input increase.

Перевод пока недоступен