Schmitt Trigger based SRAM Cell for Ultralow Power Operation- A CNFET based Approach

Embedded cache built using SRAM cells forms an integral part of system-on-chips. Many modifications for low power operation of the SRAM cell have been proposed in the recent past. In order to lower power consumption and to obtain process variation tolerance a Schmitt trigger based differential sensing SRAM cell has been proposed recently. Meanwhile with scaling transistors and interconnects pushing the limits for conventional CMOS transistors, the Carbon Nanotube Field Effect Transistors(CNFET) has been considered for high performance, high stability circuits at the cost of low power as an viable alternative to silicon recently. Hence this paper proposes a CNFET based Schmitt trigger SRAM cell for ultralow power operation and to attain process variation tolerance. The simulation results using the Stanford CNFET model proves that there is a 54x reduction in the dynamic power consumed by the cell when compared to convention 6T SRAM cell.

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