Статья

Scaling of Nanowire Transistors

Bo YuDepartment of Electrical and Computer Engineering, University of California, La Jolla, CA, USALingquan WangDepartment of Electrical and Computer Engineering, University of California, La Jolla, CA, USAYuan YuDepartment of Electrical and Computer Engineering, University of California, La Jolla, CA, USAP.M. AsbeckDepartment of Electrical and Computer Engineering, University of California, La Jolla, CA, USAYuan TaurDepartment of Electrical and Computer Engineering, University of California, La Jolla, CA, USA

2008en

ABI

Аннотация

This paper considers the scaling of nanowire transistors to 10-nm gate lengths and below. The 2-D scale length theory for a cylindrical surrounding-gate MOSFET is reviewed first, yielding a general guideline between the gate length and the nanowire size for acceptable short-channel effects. Quantum confinement of electrons in the nanowire is discussed next. It gives rise to a ground-state energy and, therefore, a threshold voltage dependent on the radius of the nanowire. The scaling limit of nanowire transistors hinges on how precise the nanowire size can be controlled. The performance limit of a nanowire transistor is then assessed by applying a ballistic current model. Key issues such as the density of states of the nanowire material are discussed. Comparisons are made between the model results and the published experimental data of nanowire devices.

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Идентификаторы

DOI: 10.1109/ted.2008.2005163

Цитирования и источники

Цитирований: 3Использованных источников: 0

Показатели — AkademScholar