Physical origin of negative differential resistance in SOI transistors
Liam McDaidDepartment of Electrical Engineering & Electronics, University of Liverpool, PO Box 147, Brownlow Hill, Liverpool, L69 3BX, UKSteven HallDepartment of Electrical Engineering & Electronics, University of Liverpool, PO Box 147, Brownlow Hill, Liverpool, L69 3BX, UKPhil MellorDepartment of Electrical Engineering & Electronics, University of Liverpool, PO Box 147, Brownlow Hill, Liverpool, L69 3BX, UKW. EcclestonDepartment of Electrical Engineering & Electronics, University of Liverpool, PO Box 147, Brownlow Hill, Liverpool, L69 3BX, UKJ. AldermanDepartment of Electrical Engineering & Electronics, University of Liverpool, PO Box 147, Brownlow Hill, Liverpool, L69 3BX, UK
1989en
ABI
Аннотация
From a two-dimensional solution of Laplace's equation it is shown that a significant increase in temperature occurs in the channel of SOI transistors due to the relatively poor thermal conductivity of the buried insulator. Based on this simulation an equation is derived which predicts that at small channel lengths the pinchoft point is shifted, an effect which is consistent with experimental observations. In addition, the positive 'kink' is reduced with increasing gate voltage and this effect, together with the negative differential resistance, can be explained by a temperature increase in the channel.
Перевод пока недоступен
Идентификаторы
Цитирования и источники
Цитирований: 5Использованных источников: 0