FPGA implementation of a linear systolic array for speech recognition based on HMM

The history of speech recognition refers to some decades ago. Speech recognition performs by using a number of complicated algorithms. Real-time and rapid execution of these algorithms is very important. In this paper, a linear systolic architecture is proposed which can execute speech recognition algorithms based on Hidden Markov Model (HMM) in parallel and pipeline forms. The proposed architecture is very regular, consisting of a set of identical and simple processor elements, which are connected together locally. In order to evaluate the proposed architecture, it has been designed by using VHDL code and synthesized on FPGA (Vertix2p) running at 320.546 MHZ.

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