DiSCERN: Distilling Standard-Cells for Emerging Reconfigurable Nanotechnologies

Recent attempts on circuits based on emerging reconfigurable nanotechnologies have primarily focused on using the traditional CMOS design flow involving similar-styled standard-cells. In the present work, we show that logic gates which implement self-dual functions can be efficiently implemented using reconfigurable nanotechnologies. We propose an algorithm which analyses the truth-tables of cuts in a mapped circuit to list all such potential reconfigurable logic gates for a particular circuit. Technology mapping with these new logic gates (or standard-cells) leads to a better mapping in terms of area and delay. Experiments employing our methodology over EPFL benchmarks, show average improvements of around 13%, 16% and 11.5% in terms of area, number of edges and delay respectively as compared to the conventional CMOS-centric standard-cell based mapping.

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