Ultimate Pixel Based on a Single Transistor With Deep Trapping Gate

Simulation results are reported on the trapping MOS structure, which is a new metal insulator semiconductor pixel concept. Using a quantum well (QW) as a buried gate, I will show that this device is the ultimate design for photon sensitive pixels when pixel size is the criterion. The device reduces to only one transistor, which acts as a charge collecting device and amplifier and it is randomly addressable. I study here the device based on a silicon-germanium material couple, but the principle can be implemented with other materials. The photo-generated charge is collected by a buried gate based on a QW, and is able to selectively localize carriers that modulate the source-drain current in the readout mode. The device simulation is based on the quantum density gradient method, which had shown to give good results with respect to previous experimental studies. They are applied in the case of thin (20 nm) buried SiGe layers, which is comparable with an earlier structure using traps for charge retention. The simulation of this structure based on actual silicon germanium technologies is robust enough to assess the practical feasibility of the device. Downscaling to deep submicrometer sizes is possible with favorable consequences regarding the pixel's sensitivity.

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