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Иш: Investigation of Ways of Synthesizing Concurrent Error-Detection Circuits Based on Boolean Signal Correction Using Uniform Separable Codes

  1. Self-dual parity checking-A new method for on-line testing

    V.V. Saposhnikov, А. Л. Дмитриев, M. Goessel +1

    Мақола200212 иқтибос
    ABI
  2. Hidden Fault Analysis of FPGA Projects for Critical Applications

    Oleksandr Drozd, Ihor Perebeinos, Oleksandr Martynyuk +3

    Мақола20208 иқтибос
    ABI
  3. Logic Complement, a New Method of Checking the Combinational Circuits

    M. Gessel', Alexandre V. Morozov, Vladimir Sapozhnikov +1

    Мақола20034 иқтибос
    ABI
  4. Checking Combinational Circuits by the Method of Logic Complement

    M. Goessel, Alexandre V. Morozov, Vladimir Sapozhnikov +1

    Мақола20054 иқтибос
    ABI
  5. CICADA: A New Tool to Design Circuits with Correction and Detection Abilities

    A. L. Stempkovsky, T.D. Zhukova, Dmitry Telpukhov +1

    Мақола20214 иқтибос
    ABI
  6. New self-checking circuits by use of Berger-codes

    Alexandre V. Morozov, V.V. Saposhnikov, V.V. Saposhnikov +1

    Мақола20023 иқтибос
    ABI
  7. Which concurrent error detection scheme to choose ?

    Subhasish Mitra, E.J. McCluskey

    Мақола20023 иқтибос
    ABI
  8. Parity driven reconfigurable duplex system

    Jaroslav Borecký, Martin Kohlík, Hana Kubátová

    Мақола20173 иқтибос
    ABI
  9. Top Level Diagnostic Models of Complex Objects

    Stanislav Mikoni

    Боб20222 иқтибос
    ABI
  10. New Methods of Concurrent Checking

    Gössel, Michael

    Китоб20082 иқтибос
    ABI
  11. Сарлавҳасиз

    Бошқа1 иқтибос
    ABI
  12. Сарлавҳасиз

    Бошқа1 иқтибос
    ABI
  13. Сарлавҳасиз

    Бошқа1 иқтибос
    ABI