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Иш: Investigation of Ways of Synthesizing Concurrent Error-Detection Circuits Based on Boolean Signal Correction Using Uniform Separable Codes
Self-dual parity checking-A new method for on-line testing
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Мақола200212 иқтибосABIHidden Fault Analysis of FPGA Projects for Critical Applications
Oleksandr Drozd, Ihor Perebeinos, Oleksandr Martynyuk +3
Мақола20208 иқтибосABIChecking Combinational Circuits by the Method of Logic Complement
M. Goessel, Alexandre V. Morozov, Vladimir Sapozhnikov +1
Мақола20054 иқтибосABINew self-checking circuits by use of Berger-codes
Alexandre V. Morozov, V.V. Saposhnikov, V.V. Saposhnikov +1
Мақола20023 иқтибосABIWhich concurrent error detection scheme to choose ?
Subhasish Mitra, E.J. McCluskey
Мақола20023 иқтибосABIParity driven reconfigurable duplex system
Jaroslav Borecký, Martin Kohlík, Hana Kubátová
Мақола20173 иқтибосABI