Design and Simulation of Four-Stage FinFET Amplifier

The proliferation of power-sensitive applications, such as wearable biomedical devices, IoT sensor networks, and high-resolution ADCs, necessitates multistage operational amplifiers that deliver high gain and wide bandwidth while driving large capacitive loads (e.g., 500pF) with minimal power dissipation. Conventional compensation techniques, such as the Negative Capacitance Generator (NCG) in [Chandra and Bansal, 2023], rely on active transistors to reduceparasitic capacitance, achieving a gain-bandwidth product (GBW) of 35.82 MHz and a phase margin of 86.68° in a 0.18µm CMOS process, but at the cost of 1.67 mW power consumption due to additional bias currents and a 1.8V supply. This work proposes a four-stage CMOS amplifier that eliminates the NCG’s active components, instead employing a dual passive compensation strategy in 16nm FinFET technology to optimize power efficiency and performance. The design integrates a primary Miller capacitor (Cc = 0.05pF) with a series resistor (Rc = 1kΩ) from the second stage output to the inverting input, creating an LHP zero to stabilize the system, and a secondary capacitor (Cn = 0.03pF)directly from the inverting input to the same node, enhancing GBW through feedforward coupling. Leveraging FinFETs’ superior trans-conductance (gm) and reduced gate capacitance, simulations in Cadence Virtuoso yield a DC gain of 165 dB, a GBW of 55 MHz, and a phase margin of 87°, with power consumption reduced to 0.8 mW under a 1V supply—a 50% improvement over the baseline. This approach minimizes thermal noise, simplifies layout complexity in deep-submicron nodes, and ensures robust stability across process variations, positioning it as a scalable solution for next-generation low-power analog circuits.

Ҳали таржима қилинмаган