Ultra-Low Power VLSI Architecture for Edge AI-based Biomedical Signal Processing

This research presents a new architecture for edge AI-enabled biomedical signal processing using extremely low powered hardware (VLSI). The architectural design involved the integration of the following components: 1) a low-noise analog front end; 2) an energy-efficient analog-to-digit converter; and 3) a small footprint neural accelerator optimized for fixed-point and approximate arithmetic. The architecture achieves low power consumption through the use of dynamic voltage and frequency scaling, fine-grained clock gating, exploiting sparsity within data, and limiting the active processing to clinically relevant times through event-driven activation. The three-layered memory architecture also serves to reduce data movement and use on-chip data compression and adaptive sampling to reduce data throughput. The architecture was designed to execute workloads for ECG, EEG, and PPG signals while providing latency-optimized inference under stringent power budgets. Validation was accomplished through the use of a combination of cycle-accurate simulations combined with silicon-aware energy models to quantify the trade-offs between accuracy, latency, and energy. The results indicate that there are significant energy savings relative to traditional edge designs while meeting all clinical performance targets. Future efforts will include prototypes suitable for mass production and clinical validation.

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