Jagdish Prasad Ahirwar

1 ta ish

Department of Mechanical Engineering, IES College Of Technology, Bhopal, MP 462044 India

1. Approximate Multiplier based on Low power and reduced latency with Modified LSB design

   K.K. Senthil Kumar, R. Vignesh, V.R. Vivek +3

   MaqolaLow-power high-performance VLSI designE3S Web of Conferences20230 iqtibos

   ABIABI:AkademIndex/openalex/2023.article.001892