Third‐order digital phase‐locked loop with improved stability

Abstract When a signal from a moving source is received by a phase‐locked loop (PLL), the input‐signal frequency of the PLL often changes in a ramp‐function state with a constant‐frequency offset. In such a case, a perfect third‐order PLL is needed to track the signal without steady‐state phase error. The conventional perfect‐integration third‐order PLL has a serious problem of being unstable for small‐amplitude inputs, and thus it cannot be used in practice in a low SNR environment. This paper proposes three types of stable perfect third‐order digital PLL's (M‐DPLL) which are independent of the input‐signal amplitude. This M‐DPLL realizes the perfect third‐order behavior by combining three first‐order DPLLs using a digital signal processing technique. The excellent characteristics of this M‐DPLL are confirmed by theoretical analysis and computer simulation.

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