Simulation processor “SP”

Abstract The continuing development of large‐scale and complicated computer systems has created an increasing demand for fast logic simulation which can locate errors in the logic design. The authors have devised a new scheme which makes use of memory instead of registers in controlling the pipeline system. This idea formed the basis for developing a new simulation processor, the “SP”. The SP is a system dedicated for simulation which performs parallel processing using up to 64 gate processors (GP). Using a newly devised pipeline control for each processor delivers high‐speed and inexpensive simulation. By combining processors with a high‐speed switch called ET, the degradation of processing speed due to the delay of information transmission in parallel processing can be prevented. The desired goal was achieved with the construction of the SP, a logic circuit with 4 million gates in which 32 Mbytes of memory could be simulated at high speed.

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