Analytical modelling and device design optimisation of epitaxial layer‐based III–V tunnel FET

The line tunnelling and heterojunction are two important techniques to improve the performance of the tunnelling field‐effect transistors (TFETs). The TFETs that utilise both of these techniques perform superior to the conventional TFETs. The recently proposed T‐shaped TFET (TTFET) is one such heterojunction‐based line tunnelling device that is expected to become energy efficient switch. For the first time, a physics‐based analytical model for surface potential and drain current of epitaxial layer‐based heterojunction line TFET has been developed. The model describes the impact of device design parameters on the electrical performance of the device. The Poisson equation is solved with precise boundary conditions to obtain the surface potential model. Kane's model is used to calculate drain current by utilising surface potential model. A good agreement between Synopsys technology computer‐aided design simulation and analytical model is observed with 5.4% error in on current at V GS = V DS = 0.5 V, an average error of 5.80% in surface potential and 7.24% in transconductance. Finally, a device design guideline is presented according to the analytical expressions.

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