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An Interface ASIC for MEMS Disk Resonator Gyroscope With 0.018°/h Bias Instability and 108 ppm Scale Factor Nonlinearity

Wenbo ZhangDepartment of Microelectronics, MEMS Center, Harbin Institute of Technology, Harbin, ChinaXin YuDepartment of Microelectronics, MEMS Center, Harbin Institute of Technology, Harbin, ChinaYihang WangDesign Institute of Electro-Mechanical Engineering, Beijing, ChinaHaifeng ZhangDepartment of Microelectronics, MEMS Center, Harbin Institute of Technology, Harbin, ChinaXuejun ShaSchool of Electronics and Information Engineering, Harbin Institute of Technology, Harbin, ChinaXiaowei LiuDepartment of Microelectronics, MEMS Center, Harbin Institute of Technology, Harbin, ChinaLiang YinDepartment of Microelectronics, MEMS Center, Harbin Institute of Technology, Harbin, ChinaQiang FuDepartment of Microelectronics, MEMS Center, Harbin Institute of Technology, Harbin, ChinaXiangyu LiNingbo Institute of Digital Twin, Eastern Institute of Technology, Ningbo, China

2025en

ABI

Annotatsiya

This paper presents a monolithic interface application-specific integrated circuit (ASIC) for a MEMS disk resonator gyroscope (DRG) with low zero-rate output (ZRO) drift and low scale factor (SF) nonlinearity. The ASIC is implemented under a high-precision force-to-balanced (FTR) mode combined with an easily integrable self-excitation drive loop. The ASIC improves the performance in two ways: First, based on an analysis of electrical errors in MEMS DRG performance, a time-domain anti-coupling architecture is proposed to reduce electrical coupling effects on ZRO drift and SF nonlinearity. This architecture also eliminates the need for high-bandwidth signal processing compared to traditional frequency-domain architectures. Second, the first-order linear relationship between ZRO drift and drive amplitude voltage in the FTR mode is analyzed and validated, and a low hardware compensation circuit is designed to correct ZRO drift. The ASIC is fabricated using a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.35\mu $</tex-math> </inline-formula> m BCD process with a chip area of 4.3 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times 4.2$</tex-math> </inline-formula> mm. Combined with the MEMS structure, it achieves a bias instability (BI), angle random walk (ARW), and SF nonlinearity of 0.018°/h, 0.0055° h, and 108 ppm, respectively.

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Identifikatorlar

DOI: 10.1109/tcsi.2025.3596470

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