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Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm

Sylvain BarraudLETI, Commissariat à l'Energie Atomique et aux Energies Alternatives, Grenoble, FranceMatthieu BerthoméLETI, Commissariat à l'Energie Atomique et aux Energies Alternatives, Grenoble, FranceR. CoquandLETI, Commissariat à l'Energie Atomique et aux Energies Alternatives, Grenoble, FranceM. CasséLETI, Commissariat à l'Energie Atomique et aux Energies Alternatives, Grenoble, FranceT. ErnstLETI, Commissariat à l'Energie Atomique et aux Energies Alternatives, Grenoble, FranceM.-P. SamsonLETI, Commissariat à l'Energie Atomique et aux Energies Alternatives, Grenoble, FranceP. PerreauLETI, Commissariat à l'Energie Atomique et aux Energies Alternatives, Grenoble, FranceK.K. BourdelleSOITEC S.A., Bernin, FranceO. FaynotLETI, Commissariat à l'Energie Atomique et aux Energies Alternatives, Grenoble, FranceT. PoirouxLETI, Commissariat à l'Energie Atomique et aux Energies Alternatives, Grenoble, France

2012en

ABI

Annotatsiya

In this letter, we report the performance of high-κ /metal gate nanowire (NW) transistors without junctions fabricated with a channel thickness of 9 nm and sub-15-nm gate length and NW width. Near-ideal subthreshold slope (SS) and extremely low leakage currents are demonstrated for ultrascaled gate lengths with a high on-off ratio (I on /I off ) >; 10 6 . For the first time, an SS lower than 70 mV/dec is achieved at LG = 13 nm for n-type and p-type transistors, highlighting excellent electrostatic integrity of trigate junctionless NW MOSFETs.

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Identifikatorlar

DOI: 10.1109/led.2012.2203091

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