Statistical variability and reliability in nanoscale FinFETs
Xingsheng WangDevice Modelling Group, School of Engineering, University of Glasgow, Glasgow, UKA. R. BrownDevice Modelling Group, School of Engineering, University of Glasgow, Glasgow, UKB. ChengDevice Modelling Group, School of Engineering, University of Glasgow, Glasgow, UKAsen AsenovDevice Modelling Group, School of Engineering, University of Glasgow, Glasgow, UK
2011en
ABI
Annotatsiya
A comprehensive full-scale 3D simulation study of statistical variability and reliability in emerging, scaled FinFETs on SOI substrate with gate-lengths of 20nm, 14nm and 10nm and low channel doping is presented. Excellent electrostatic integrity and resulting tolerance to low channel doping are perceived as the main FinFET advantages, resulting in a dramatic reduction of statistical variability due to random discrete dopants (RDD). It is found that line edge roughness (LER), metal gate granularity (MGG) and interface trapped charges (ITC) dominate the parameter fluctuations with different distribution features, while RDD may result in relatively rare but significant changes in the device characteristics.
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