The synthesis of self-checking combinational devices based on properties of codes with summation of weighted transitions and selection of testable outputs groups

The article covers the issues of the synthesis of self-checking discrete systems. The authors introduced the method of building modified codes with summation of weighted transitions between the bits taking neighboring positions in data vectors. The new codes with summation possess the same number of check bits as classical Berger codes, but detect more errors in data vectors. Modified codes with summation of weighted transitions, similar to Berger codes, possess high performance of detecting errors of low multiplicity. Moreover, for some values of data vectors' lengths there may be built codes with detection of all double and all triple errors. Such codes may effectively be applied in logical units' control organization. The authors developed the method of synthesis of concurrent error-detection (CED) systems of combinational circuits', based on the analysis of the unit under test topology with selection of groups of testable outputs taking into account the error detecting properties of modified codes with summation of weighted transitions. An algorithm of CED system's synthesis was formed.

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