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Self-Dual Complement Method up to Constant-Weight Codes for Arrangement of Combinational Logical Circuits Concurrent Error-Detection Systems

Д.В. ЕфановRemote Control and Communication on Railway Transport”, Russian University of Transport, Moscow, RussiaValery SapozhnikovAutomation and Remote Control on Railways Department, Emperor Alexander I St. Petersburg State Transport University, St. Petersburg, RussiaVladimir SapozhnikovAutomation and Remote Control on Railways Department, Emperor Alexander I St. Petersburg State Transport University, St. Petersburg, RussiaGerman OsadchyD.V. PivovarovAutomation and Remote Control on Railways Department, Emperor Alexander I St. Petersburg State Transport University, St. Petersburg, Russia
2019en
ABI

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Authors of this article are being recommended a new approach to concurrent checking method arrangement, composed of main features of Self-Dual Complement Method together with constant-weight code. According to analysis we may state that in the event of single control application based on self-dual function characteristic either via being arranged digital word to constant-weight code, some errors of comprised circuit may not be detected. Unification procedure while functional control of two characteristics helps us to advance the whole concurrent error-detection (CED) system regarding errors identification. In this article we are presenting realization method of concurrent checking in accordance with Self-Dual Complement Method up to constant-weight code. It was demonstrated that to ensure supervision characteristic per two symptoms of the system we may apply constant-weight code `r out of 2r' (r - weight value of the digital word of the constant-weight code). In this case, the developed via authors method of CED system arrangement considered self-dual features for each function of the constant-weight code words. The most effective instrument in this approach is reckoned code `2 out of 4' with simple checker structure for the purpose of the entire check out of few coded combinations. In the event of multiple outputs circuits those exit ports should be divided per four groups for each of those matrices and outputs of separate control circuits must be unified upon self-checkable comparator output. The above-mentioned option allowed us to widen the aforementioned way to synthesis of combinational circuits under supervision.

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