New Self‐dual Circuits for Error Detection and Testing
А. Л. ДмитриевUniversity of Potsdam, Department of Computer Science, Fault Tolerant Computing Group, PSF 601553, Potsdam D-14415V. SaposhnikovRailway Transportation State University, Moskovskij pr. 9, SU190031 St.-PetersburgV.V. SaposhnikovRailway Transportation State University, Moskovskij pr. 9, SU190031 St.-PetersburgM. GoesselUniversity of Potsdam, Department of Computer Science, Fault Tolerant Computing Group, PSF 601553, Potsdam D-14415Vl. MoshaninUniversity of Potsdam, Department of Computer Science, Fault Tolerant Computing Group, PSF 601553, Potsdam D-14415A. MorosovUniversity of Potsdam, Department of Computer Science, Fault Tolerant Computing Group, PSF 601553, Potsdam D-14415
1999en
ABI
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In this paper new methods for the transformation of a given combinational circuit into a self‐dual circuit based on the notion of a self‐dual complement are investigated. The large variety of self‐dual complements can be utilized to optimize the transformed self‐dual circuit. Self‐dual duplication and self‐dual parity prediction are considered in detail. As a method for the reduction of self‐dual outputs, output space compaction of self‐dual outputs is considered. For the first time we also describe in this paper how a self‐dual circuit can be modified into a self‐dual fault‐secure circuit.
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