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Method for Testing Combinational Circuits by Multiple Diagnostic Features Using Weight-Based Sum Codes Properties

Д.В. ЕфановHigher School of Transport, Institute of Machinery, Materials and Transport, Peter the Great St. Petersburg Polytechnic University, St. Petersburg 195251, RussiaD.V. Pivovarov“Automation and Remote Control on Railways” Department, Emperor Alexander I St. Petersburg State Transport University, St. Petersburg 190031, RussiaNicolás Cortegoso VissioLaboratory “Industrial Stream Data Processing Systems”, School of Advanced Engineering Studies in Digital Engineering, Peter the Great St. Petersburg Polytechnic University, St. Petersburg 195251, RussiaAlexander O. KuptsovLaboratory “Industrial Stream Data Processing Systems”, School of Advanced Engineering Studies in Digital Engineering, Peter the Great St. Petersburg Polytechnic University, St. Petersburg 195251, RussiaDaniil E. EgorovLaboratory “Industrial Stream Data Processing Systems”, School of Advanced Engineering Studies in Digital Engineering, Peter the Great St. Petersburg Polytechnic University, St. Petersburg 195251, Russia
2025en
ABI

Annotatsiya

The paper puts forth a methodology for the arrangement of calculation control at the outputs of combinational digital devices based on utilizing multiple diagnostic features. The first diagnostic feature is the belonging of the formed codewords to a pre-selected weight-based sum code. The second and third diagnostic features are the control of calculations by the belonging of calculated functions describing data and checking bits of sum codes to the class of self-dual and related functions. The arrangement of calculation control by multiple diagnostic features is founded upon the implementation of Boolean signal correction during the synthesis of the embedded control circuit. This is conducted in consideration of the established characteristics of weight-based sum codes, wherein the functions describing their checking bits exhibit identical values on pairs of data vectors inversed in all bits (these are the so-called self-quasidual functions). The utilization of Boolean signal correction on the orthogonal to all input variable combinations enables the additional determination of correction function values. This ensures the self-duality of functions describing data bits and, consequently, the self-quasiduality of functions describing checking bits. The paper proposes a structure for arranging the calculation control in accordance with the three specified diagnostic features. Furthermore, it develops the algorithm of correction function additional determination that underlies the synthesis of the embedded control circuit. It should be noted that the algorithm does not require the analysis of the values of functions calculated at the outputs of the object of diagnostics; instead, it automatically allows for the performance of additional determinations. This facilitates its utilization when integrated with computer-aided logic design systems. The paper presents a case study of the process of obtaining correction functions and simulates the operation of the synthesized self-checking device, thereby demonstrating the effectiveness of the proposed method.

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