Efficient FPGA‐based VLSI architecture for detecting R‐peaks in electrocardiogram signal by combining Shannon energy with Hilbert transform

Electrocardiogram (ECG) is a critical application in light of R‐peak detection. The R‐peaks are impacted by some QRS complex and noises in the current method. Basic testability, snappier execution, and confirmation choices are accomplished by the utilization of the field programmable gate array (FPGA). But, FPGA execution gives less accuracy. To battle execution trouble, another R‐peak detector is proposed and relying upon the propelled peak finding logic, which incorporates a Bandpass filter and first‐order differentiation process, which are done in the primary phase of the strategy. The noises in the input ECG signal are decreased in the first stage. In the subsequent stage, the smooth Shannon energy envelope (SEE) is acquired by utilizing SEE extraction and the zero phases filtering process. The false R peak is stifled by proposing a Hilbert transform (HT) in the third stage. The HT requires more hardware space and high‐power utilization in the current technique. Due to this reason, Real valued Fast Fourier Transform (RFFT) and Inverse RFFT (IRFFT) techniques are proposed in the HT. In the fourth stage, R‐peak acknowledgment is evaluated using Massachusetts Institute of Technology, Beth Israel Hospital (MIT‐BIH) arrhythmia database and produced the average accuracy of 99.86%, sensitivity of 99.95% and the positive predictivity of 99.90%.

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