Design and Optimization of a CMOS Inverter-Based Low-Noise Amplifier for Enhanced Gain and Efficiency in Wearable Electronics

The rapid advancement of wearable devices has driven the need for highly efficient, low-noise amplifiers (LNAs).This study presents a novel LNA architecture leveraging CMOS inverter topologies to achieve superior performance in gain, noise reduction, and energy efficiency.The key innovation lies in the optimized use of CMOS inverters, which enhance signal amplification while minimizing power consumption.Compared to existing designs, the proposed LNA exhibits a reduced noise figure (NF) of 2.6 dB, a high voltage gain of 30 dB, and operates at ultra-low power levels, making it ideal for energy-constrained applications.Fabricated using standard complementary metal-oxide semiconductor (CMOS) technology, the LNA is optimized for pulsed nanoampere-level currents, such as those generated by Si-based light-emitting sensors.The circuit is meticulously designed to mitigate parasitic effects, employing a layout-aware optimization framework to ensure robust performance under varying conditions.Operating at a low supply voltage of 1.2 V with a current requirement of just 1 A, the LNA is particularly well-suited for biomedical and wearable electronics.To validate its performance, post-layout simulations assess key parameters, demonstrating significant improvements over state-of-the-art designs.Comparative analysis highlights the LNA's efficiency in signal integrity and low-power operation, making it an optimal choice for next-generation sensor networks and medical applications.By addressing critical design challenges, this study provides a comprehensive analysis of an advanced LNA architecture, offering new insights into the development of high-performance amplifiers for modern electronic systems.

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