Hardware accelerators for solving computationally intensive problems over binary vectors and matrices
Abstract
The paper selects reusable operations over binary and ternary vectors that are frequently used in many important practical applications (that are explicitly indicated) and suggests methods to implement them in hardware accelerators. Many examples are given. The developed architectures are organized as either combinational or sequential designs. The following steps are elaborated: 1) suggesting methods and architectures based on knowledge and the results of previous publications; 2) modeling in software and estimating the most important characteristics of the future circuits; 3) implementation in hardware, evaluation of the design, and experiments. The presented example demonstrates all these steps. The results of experiments show effectiveness of the proposed accelerators form the point of view of performance and the consumed resources.