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Efficient two-pair-two-rail checker design using quantum dot cellular automata for nanoprocessors

Angshuman KhanDepartment of Electronics & Communication Engineering, University of Engineering & Management, Jaipur, Rajasthan-303807, IndiaNuriddin SafoevDepartment of Cybersecurity and Forensics, Tashkent University of Information Technologies named after Muhammad Al-Khwarizmi, Tashkent-100200, UzbekistanR. ShawDepartment of Electronics & Communication Engineering, University of Engineering & Management, Jaipur, Rajasthan-303807, IndiaDilfuza MaxmudovaDepartment of Methods of Teaching Mathematics and Geometry, Chirchik State Pedagogical University, Tashkent-111700, UzbekistanSanjar MardovDepartment of Engineering Graphics and Computer Design, Tashkent University of Architecture and Civil Engineering, Tashkent-100194, UzbekistanNilufar IsakulovaDepartment of Pedagogy and Psychology, Uzbek State World Languages University, Tashkent-100173, Uzbekistan
Physica Scriptajournal2025en
ABI

Abstract

Abstract Quantum-dot Cellular Automata (QCA) is a promising approach for nanoscale circuit design, particularly in nanoprocessors and nano-computation through Conservative logic, which helps to mitigate data loss in modern small-size processors by ensuring equal inputs and outputs. This work presents a new Conservative QCA (CQCA) layout that improves cell count by 35% and reduces area by 50% compared to the best existing design. The CQCA facilitates the identification of parity faults in QCA nano-processors through the utilization of a testable block (TB). Consequently, a CQCA-based TB is developed in QCA utilizing majority and minority logic, attaining 1.5 times superior area efficiency compared to the relevant prior design. The TB is subsequently utilized in a Two-Pair-Two-Rail Checker (2P2RC) to illustrate its practical usefulness. This study presents a QCA configuration for 2P2RC and evaluates its efficacy. Energy and cost assessments indicate that the revised layouts enhance efficiency in critical performance parameters. These designs enhance nano-architecture by assessing memory module and data bus performance, guaranteeing reliable data transfer, and preserving signal integrity between paired circuits to avert signal loss.

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