Dynamic Scheduling Resource Scaling and Adaptive LSQ Co-Optimization for Energy Efficiency

Abstract

Advanced microprocessor designs enhance memory-level parallelism through large-scale scheduling resources. However, fixed-configuration scheduling resources induce significant energy overhead. To address this challenge, this study presents a collaborative optimization approach spanning microarchitecture and circuit levels, integrating a resource bottleneck dynamic scaling strategy with an adaptive Load-Store Queue. The proposed scheme dynamically adjusts the scale of scheduling resources by monitoring performance bottlenecks induced by scheduling resources during program execution. Experimental results demonstrate a 27.9% energy reduction across SPEC CPU2017 benchmarks and a 35.6% reduction in Graph Algorithm Platform Benchmark Suite.

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Identifiers

DOI

10.1109/icta68203.2025.11330114

Citations and references