A Cryogenic 1024-Channel Mixed-Signal ASIC for SiPM Readout in 110 nm CMOS for the GRAIN Detector at DUNE
Аннотация
This paper presents a cryogenic 1024-channel mixed-signal ASIC under development at INFN for the GRAIN detector at the DUNE Near Detector complex at Fermilab. GRAIN is a 1 -ton LAr detector that reconstructs charged particle tracks from neutrino interactions via scintillation light. The ASIC reads out 32 × 32 SiPM matrices and handles highly piled-up photon events in 10 μs acquisition windows every 1.2 s, ensuring sub-200ps time tagging and photon counting for accurate track reconstruction. Events separated by over 100 ns must be distinguished. The ASIC, to be fabricated in a 110 nm CMOS process with a 1.2 V supply, leverages silicon-proven IP blocks and cryogenic characterization from a prior 32-channel ASIC. Occupying nearly the full 2 cm × 3 cm reticle area, it integrates 1024 pixel channels, end-of-column SRAM, control logic, and 32 SLVS transceivers, enabling an aggregate bandwidth up to 40 Gbps. Each channel includes a current conveyor front-end with separate timing and charge integration paths. The timing chain includes transimpedance amplifiers and dual-threshold discriminators supporting time-overthreshold and slew-rate measurements for time-walk correction. Four on-pixel TDCs use analog interpolation with an 8-bit SAR conversion algorithm, achieving a 20 ps LSB and 30 ns conversion time at 87 K, with minimal event loss through derandomization. Photon counting is enabled via a current-to-frequency converter for real-time charge digitization. I/O pads are distributed in a 500 μm-pitch grid across the chip, with flip-chip BGA packaging using an highly-matched CTE interposer for cryogenic compatibility. Chip integration is underway, with verification expected to conclude by late 2025, followed by submission for the first engineering run.