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Fabrication and Characterization of Stacked Poly-Si Nanosheet With Gate-All-Around and Multi-Gate Junctionless Field Effect Transistors

Meng‐Ju TsaiDepartment of Engineering and System Science, National Tsing Hua University, Hsinchu, TaiwanKang-Hui PengDepartment of Engineering and System Science, National Tsing Hua University, Hsinchu, TaiwanChong-Jhe SunDepartment of Engineering and System Science, National Tsing Hua University, Hsinchu, TaiwanSiao-Cheng YanDepartment of Engineering and System Science, National Tsing Hua University, Hsinchu, TaiwanChieng-Chung HsuDepartment of Engineering and System Science, National Tsing Hua University, Hsinchu, TaiwanYu-Ru LinDepartment of Electronic Engineering, National United University, Miaoli, TaiwanYu-Hsien LinDepartment of Electronic Engineering, National United University, Miaoli, TaiwanYung‐Chun WuDepartment of Engineering and System Science, National Tsing Hua University, Hsinchu, Taiwan
2019en
ABI

Аннотация

Present work demonstrates the vertically double stacked nanosheet (NS) p-channel polycrystalline silicon (poly-Si) junctionless field-effect transistors (JL-FET) with tri-gate, omega-gate, and gate all around (GAA) structure. These structures offer more W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> per existing footprint and better parallel resistance, resulting in smaller total resistance. Also, the GAA stacked NS device shows superior electrical properties, including high Ion/Ioff ratio (> 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> ), steep subthreshold swing (SS) = 100 mV/dec, very low drain-induced-barrier-lowering (DIBL) = 0.127 mV/V and usually off at Vg = 0 V, owing to superior gate controllability. More, the 3D TCAD simulation has applied for analysis of physical characteristics of the proposed devices.

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