Jagdish Prasad Ahirwar

1 ta ish

Madhya Pradesh Council of Science and Technology

1. Approximate Multiplier based on Low power and reduced latency with Modified LSB design

   K.K. Senthil Kumar, R. Vignesh, V.R. Vivek +3

   MaqolaOAOchiq kirishLow-power high-performance VLSI designE3S Web of Conferences20230 iqtibos

   ABIABI:AkademIndex/2023.article.001892