Low-power high-performance VLSI design

19 ta ish

1. Design and Implementation of Selective Adaptive Pipeline Structure for Low Power RISC Processor Applications

   Omprakash Gurrapu, Sudha Rajesh, Raxmanov Jurabek +5

   MaqolaEmbedded Systems Design Techniques20251 iqtibos

   ABIABI:AkademIndex/2025.article.001830

2. Design and Simulation of Four-Stage FinFET Amplifier

   Jami Venkata Suman, P.Anitha, Jaya sudha reddy +3

   MaqolaAnalog and Mixed-Signal Circuit Design20251 iqtibos

   ABIABI:AkademIndex/2025.article.002704

3. Dynamic characteristics of the push‐pull dc‐dc converter

   Masahito Shoyama, Koosuke Harada

   MaqolaAdvanced DC-DC ConvertersElectronics and Communications in Japan (Part II Electronics)19860 iqtibos

   ABIABI:AkademIndex/1986.article.000063

4. Simulation processor “SP”

   Hiroshi Yamada, Fumiyasu Hirose, Junichi Niitsuma +1

   MaqolaVLSI and FPGA Design TechniquesSystems and Computers in Japan19890 iqtibos

   ABIABI:AkademIndex/1989.article.000066

5. Fault tolerant and BIST design of a FIFO cell

   Fulvio Corno, P. Prinetto, M. Sonza Reorda

   MaqolaVLSI and Analog Circuit TestingPORTO Publications Open Repository TOrino (Politecnico di Torino)19960 iqtibos

   ABIABI:AkademIndex/1996.article.000062

6. A radix-10 SRT divider based on alternative BCD codings

   Álvaro Vázquez, E. Antelo, Paolo Montuschi

   MaqolaNumerical Methods and Algorithms20070 iqtibos

   ABIABI:AkademIndex/2007.article.000066

7. Simulation of Random Telegraph Noise in Nanometer nMOSFET Induced by Interface and Oxide Trapped Charge

   A. É. Atamuratov, R. Granzner, M. Kittler +3

   BobSemiconductor materials and devicesNATO science for peace and security series. B, Physics and biophysics20130 iqtibos

   ABIABI:AkademIndex/2013.chapter.000013

8. Circuits for robust designs

   Roberto Fontana, Fabio Rapallo, Wynn Henry

   PreprintOAOchiq kirishVLSI and FPGA Design TechniquesStatistical Papers20220 iqtibos

   ABIABI:AkademIndex/2022.preprint.000043

9. Performance Analysis Of SRAM and Dram in Low Power Application

   S. Yuvaraj, D. Padmanaban, G. PraveenKumar +3

   MaqolaOAOchiq kirishLow-power high-performance VLSI designE3S Web of Conferences20230 iqtibos

   ABIABI:AkademIndex/2023.article.001066

10. Approximate Multiplier based on Low power and reduced latency with Modified LSB design

    K.K. Senthil Kumar, R. Vignesh, V.R. Vivek +3

    MaqolaOAOchiq kirishLow-power high-performance VLSI designE3S Web of Conferences20230 iqtibos

    ABIABI:AkademIndex/2023.article.001892

11. Advanced Design and Fabrication Techniques for Nanoscale Semiconductor Devices in Next-Generation Electronics

    Ujjwal Kumar Singh, Raghu Gopa, Jayanth Kolli +3

    MaqolaAdvancements in Semiconductor Devices and Circuit Design20250 iqtibos

    ABIABI:AkademIndex/2025.article.010825

12. Enhancing Noise Immunity in Mixed-Signal Circuits for Biomedical Applications

    Parvindar Kaur Chhabda, R. Padmavathy, Hassan Mohamed +4

    MaqolaLow-power high-performance VLSI design20250 iqtibos

    ABIABI:AkademIndex/2025.article.018488

13. AIML-Based Accounting of Physical Constraints: Transformer Optimization for Biomedical PhC Systems

    Lisa Gopal, Lucky Verma, Shailendra Tiwari +3

    MaqolaLow-power high-performance VLSI design20250 iqtibos

    ABIABI:AkademIndex/2025.article.019124

14. Analysis of Dynamic Domino Logic Gate Performance Using Body Bias Techniques in Sub-Micron VLSI

    Ravi Kumar M, K. M. Pimple, Prabhakaran K +3

    MaqolaLow-power high-performance VLSI design20250 iqtibos

    ABIABI:AkademIndex/2025.article.019326

15. Low-Power VLSI Architecture for Continuous Wearable Health Monitoring Applications

    K. Prasannalatha, Gill Santosh Kumar, A Vani +3

    MaqolaLow-power high-performance VLSI design20260 iqtibos

    ABIABI:AkademIndex/2026.article.015806

16. FPGA-based Rapid Prototyping of High-Performance SoC Architectures

    Jami Venkata Suman, K.Surendra, Aenikapati Swetha Priya +3

    MaqolaEmbedded Systems Design Techniques20260 iqtibos

    ABIABI:AkademIndex/2026.article.017007

17. Optimization of Data Link Layer Protocol Performance in High-EMI Communication Channels

    Farruh Kushnazarov

    MaqolaAdvancements in PLL and VCO TechnologiesZenodo (CERN European Organization for Nuclear Research)20260 iqtibos

    ABIABI:AkademIndex/2026.article.019206

18. Optimization of Data Link Layer Protocol Performance in High-EMI Communication Channels

    Farruh Kushnazarov

    MaqolaOAOchiq kirishAdvancements in PLL and VCO TechnologiesZenodo (CERN European Organization for Nuclear Research)20260 iqtibos

    ABIABI:AkademIndex/2026.article.019407

19. Ultra-Low Power VLSI Architecture for Edge AI-based Biomedical Signal Processing

    Jami Venkata Suman, Aenikapati Swetha Priya, Sujatha Kotte +3

    MaqolaLow-power high-performance VLSI design20260 iqtibos

    ABIABI:AkademIndex/2026.article.023371