Y. I. Yelina

1 ta ish

Peter the Great St. Petersburg Polytechnic University

1. Synthesis of Concurrent Error-Detection Circuits Based on Boolean Signals Correction Using Modular Weight-Based Sum Codes

   Д.В. Ефанов, Y. I. Yelina

   Maqola20242 iqtibos

   ABIABI:AkademIndex/2026.other.585603