Marcelo Antonio Pavanello

3 ta ish

Faculty of Industrial Engineering

1. Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors

   Renan Trevisoli, Rodrigo T. Doria, Michelly de Souza +3

   MaqolaOAOchiq kirish201212 iqtibos

   ABIABI:AkademIndex/2026.other.228622

2. Temperature Measurement of a Nanowire SOI Transistor Using a Parallel Gated SOI PIN Diode

   Felipe Rodrigues Gare Carnielli, Marcelo Antonio Pavanello

   Maqola20242 iqtibos

   ABIABI:AkademIndex/2026.other.335610

3. Double-gate junctionless transistor model including short-channel effects

   Bruna Cardoso Paz, Fernando Avila Herrera, A. Cerdeira +1

   Maqola20152 iqtibos

   ABIABI:AkademIndex/2026.other.570273