K. M. Pimple

1 ta ish

Dr. Rajendra Gode Institute of Technology and Research,Department of Electronics and Telecommunication Engineering,Amravati,India

1. Analysis of Dynamic Domino Logic Gate Performance Using Body Bias Techniques in Sub-Micron VLSI

   Ravi Kumar M, K. M. Pimple, Prabhakaran K +3

   MaqolaLow-power high-performance VLSI design20250 iqtibos

   ABIABI:AkademIndex/openalex/2025.article.019326