Analysis of Dynamic Domino Logic Gate Performance Using Body Bias Techniques in Sub-Micron VLSI
Annotatsiya
The use of dynamic domino logic to design high-speed digital systems has become standard; however, with the more recent progress in technology to sub-micron nodes it faces huge challenges of power-delay trade-offs, reduced noise margins, and risen leakage currents. The paper explores the impact of Forward Body Bias (FBB) and Reverse Body Bias (RBB) to the functionality of domino logic circuits to address these issues. The overall aim of the study is to determine how body biasing can be utilised to optimise propagation delay and minimise leakage power in way that does not compromise on energy efficiency. It is developed using Cadence Virtuoso and HSPICE simulation and involves the construction of basic domino logic gates (AND, OR, NAND, NOR) using 65 nm CMOS technology. A number of biasing circumstances were tested in order to assess critical performance metrics, including propagation delay, average power, leakage power, and the Power-Delay Product (PDP). As RBB minimizes leakage power at a cost of time penalty, FBB significantly minimizes latency and maximizes PDP at the cost of higher leakage, as per the simulation results. The no-bias condition is a good balance as far as power and speed is concerned. The study would be useful in advising future low-power, high-speed systems by revealing the value of body biasing as a scalable design knob to optimize domino logic circuit using sub-micron VLSI technology.