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Design and simulations of the 10-bit SAR ADC in novel sub-micron technology 200 nm SOI CMOS

Roma DasguptaAGH University of Science and Technology, CracowS. BugielAGH University of Science and Technology, CracowSebastian GłąbAGH University of Science and Technology, CracowM. IdzikAGH University of Science and Technology, CracowJ. MorońAGH University of Science and Technology, CracowP. KapustaInstitute of Nuclear Physics PAN, Cracow

2014en

ABI

Annotatsiya

This paper presents the design of the 10-bit Successive Approximation Register Analog-to-Digital Converter (SAR ADC) achieving 20 MHz sampling frequency at a power consumption of about 900 μW and 1.8 V power supply. The ADC was designed in 200 nm Silicon-On-Insulator (SOI) CMOS process. The SOI is one of the most advanced CMOS technology that allows to reduce the parasitic capacitances, limit power dissipation and increase speed of the system.

Mavzular

Analog and Mixed-Signal Circuit Design Advancements in Semiconductor Devices and Circuit Design CCD and CMOS Imaging Sensors

Identifikatorlar

DOI: 10.1109/mixdes.2014.6872180

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