Fault tolerant and BIST design of a FIFO cell
Annotatsiya
This paper presents a BIST design of a parametrized FIFO component. The component is currently being used in the standard library of Italtel, the main Italian telecom circuit maker. Design choices have been strongly influenced by industrial constraints imposed by the Italtel design flow. To achieve the desired fault coverage level for faults in the memory and in the control logic, traditional BIST schemes had to be combined with more advanced testing techniques. Different parts of the circuits are tested with different strategies and algorithms to account for their different nature: critical parts of the design, such as the FIFO control unit and the BIST controller are tested with on-line test techniques. The final implementation shows that a high fault coverage is attained with an acceptable area overhead and no speed penalty.